1. Field of the Invention
The present invention relates to a bias circuit for supplying a constant voltage, and more particularly, to a new replica bias circuit which has a generator for generating a sub threshold voltage lower than a threshold voltage of a transistor, and which can be used in application fields using a low power supply voltage. For example, the present invention relates to a replica bias circuit for supplying a bias voltage to three-layer stacked CMOS current mode logic (CML) gates and latches that are widely used in integrated circuit devices.
2. Discussion of Related Art
Typical CMOS logic circuits include CMOS switches and CMOS inverters (See the above KR Patent). Such CMOS logic circuits exhibit a stable operation characteristic and have no static current, but operate at a low speed. For high-speed operation, CMOS current mode logic (CML) is used (See the above US patent). The CMOS current mode logic may have a two-layer stacked structure like an inverter or a buffer, or a three-layer stacked structure like a latch or an AND circuit. In the three-layer stacked CMOS current mode logic, when a bias voltage is supplied using a level shifter 120 according to the above US patent as shown in FIG. 1, a difference between a power supply voltage and a ground voltage should be sufficient (e.g., 1.8 V or greater) to guarantee stable operation. Otherwise, the logic becomes sensitive to PVT (process, voltage, temperature) variation.
However, the recent development of a CMOS process lowers a line width to 0.13 μm or less and a power supply voltage to 1.2 V or less. Use of the three-layer stacked CMOS current mode logic, even at a low power supply voltage, requires a suitable replica bias circuit.